ITSW 2009 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Key Dates -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 45 nanometers with smaller geometries on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools, and methodologies in all aspects of digital chip design and manufacturing. The widespread use of Test Synthesis coupled with powerful pre-silicon verification approaches is one factor that has enabled test to keep up with the increasing chip complexity.

This year ITSW moves to a new location at the University of Texas, Austin. This year’s workshop will look at all aspects of test synthesis such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No Trouble Found methods, and dealing with variations and imperfections inherent in the manufacturing process.

Key Dates

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Advance Registration Deadline: March 6th, 2009!

Workshop Registration

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Workship registration is available on the conference website (www.tttc-itsw.org), click the links on the left for Online or FAX registration. The advanced registration deadline is March 6th.

Advance Program

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Monday -- Tuesday -- Wednesday

March 23, 2009 (Monday)

7:30 AM - 8:30 AM CONTINENTAL BREAKFAST

8:30 AM - 9:45 AM	OPENING SESSION
8:30 - 8:45	Opening Message Jennifer Dworak, General Chair
8:45 - 9:45	Keynote: Test's Changing Role in the Late-Silicon Era T. Cheng (UCSB)

9:45 AM - 10:45 AM	Test Compression
9:45 - 10:15	Mask Sharing for Efficient X-Masking in Scan Compressed Designs P. Dasgupta, B. Foutz, V. Kadam, S. Bhatia, S. Mukherjee (Cadence)
10:15 - 10:45	Efficient Linear Decompression Using ATE Vector Repeat-Per-All-Pins J. Lee (Intel), N. A. Touba (UT-Austin)

10:45 AM - 11:15 AM COFFEE BREAK

11:15 AM - 12:15 PM	BIST
11:15 - 11:45	Clock Monitoring Simulations for BIST Verification S. Hwang, I. Kim, A. Guettaf (Broadcom)
11:45 - 12:15	Optimized Distributed Simulation of Logic BIST Patterns J. Udell, G. Mrugalski, T. Rinderknecht (Mentor)

12:15 PM - 1:30 PM LUNCH

11:15 AM - 12:15 PM	Delay Test
1:30 - 2:00	An Evaluation of Frequency vs Switching Activity Using At-speed Structural Patterns T. McLaurin, C. Hawkins (ARM)
2:00 - 2:30	Evaluation of Speed Path Identification of Structural Tests J. Zeng, H.-C. Yu, M. Mateja, J. Wang (AMD), Li-C. Wang (UCSB)
2:30 - 3:00	Unsensitizable Path Identification at RTL Using High-Level Synthesis Information S. Ohtake, N. Ikeda, M. Inoue, H. Fujiwara (NIST, Japan)

3:00 PM - 3:30 PM COFFEE BREAK

3:30 PM - 5:00 PM	Functional Test and Debug
3:30 - 4:00	Considering Functional Behavior for Probabilistic Defect Detection C. Ashley-Rollman, Y. Shi, J. Dworak (Brown Univ.)
4:00 - 4:30	Selecting Signals to Observe for Silicon Debug J.-S. Yang, N. A. Touba (UT-Austin)
4:30 - 5:00	Test and Debug Tools for High Lane-Count, High Speed I/O in a Production Environment P. Cadorette, J. Turek (TI)

5:00 PM - 6:30 PM	Fault Tolerance and Reliability
5:00 - 5:30	A Fault-Tolerant Technique for Analog Filters S. Askari, A. Namazi, M. Nourani (UT-Dallas)
5:30 - 6:00	Improving Memory ECC by Exploiting Unused Spare Columns R. Datta, N. A. Touba (UT-Austin)
6:00 - 6:30	3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits R. Garg, S. P. Khatri (Texas A&M)

6:30 PM DINNER (On Your Own)

March 24, 2009 (Tuesday)

7:00 AM - 8:00 AM CONTINENTAL BREAKFAST

8:00 AM - 9:00 AM	Keynote Address
	Getting More Out of Test: Addressing Variability and DFM Anne Gattiker (IBM)

9:00 AM - 10:00 AM	DFT
9:00 - 9:30	Improving Memory Repair by Selective Row Partitioning T. Rab, A. Bawa, N. A. Touba (UT-Austin)
9:30 - 10:00	A Robust Pulse-triggered Flip-flop and an Enhanced Scan Cell Design T. Soni, S. P. Khatri (Texas A&M)

10:00 AM - 10:30 AM COFFEE BREAK

10:30 AM - 11:30 PM	Industry Standards and Practices
10:30 - 11:00	Challenges in System Content Grading S. Patil (Intel)
11:00 - 11:30	P1687 2009 Update: The Story of IJTAG A. Crouch (ASSET InterTech)

11:30 AM - 3:00 PM LUNCH AND SOCIAL EVENT (CRUISE ON TOWN LAKE)

3:00 PM - 4:00 PM	Embedded Tutorial I
	The Whys and Whats of an IEEE 1500 Wrapper T. McLaurin (ARM)

4:00 PM - 4:15 PM COFFEE BREAK

4:15 PM - 6:15 PM	PANEL: Move Over Time Zero Test, On-line is Here to Stay Moderator: P. Joshi (Intel)
	Panelists: S. Patil (Intel) T. Cheng (UCSB) T. Munns T. Skergan (IBM) A. Nahar (TI)

6:30 PM DINNER (On Your Own)

March 25, 2009 (Wednesday)

7:00 AM - 8:00 AM CONTINENTAL BREAKFAST

8:00 AM - 9:30 AM	ATPG and Fault Simulation
8:00 - 8:30	Low Cost Test Generation for Delay Test Z. Wang, D. M. H. Walker (Texas A&M)
8:30 - 9:00	Fault Table Generation Using Graphics Processing Units K. Gulati, S. P. Khatri (Texas A&M)
9:00 - 9:30	Enhancement Approaches for Constant Test Power Algorithm Z. Jiang, D. M. H. Walker (Texas A&M)

9:30 AM - 10:30 AM	Embedded Tutorial II
	Coming Soon to an SoC or SiP Near You – The IEEE 1149.7 Reduced-Pin and Enhanced-Functionality Test Access Port A. Ley (ASSET InterTech)

10:30 AM - 11:00 AM COFFEE BREAK

11:00 AM - 12:00 PM	DFT
11:00 - 11:30	Column-Addressable Multiple Scan Architecture for Low Power Testing and Delay Testing S. P. Lin, C. L. Lee (NCTU, Taiwan), J.-J. Chen, K.-L. Luo, W. C. Wu (ITRI, Taiwan)
11:30 - 12:00	Low Cost Design-for-Testability Features of an Industrial Control Application SoC C. ZhiKuang, H. Kai (Southeast Univ., China)

12:00 PM - 12:15 PM	ITSW 2009 Best Student Paper Award

12:15 PM ADJOURN

More Information

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For general information, contact:
Jennifer Dworak, General Chair
Division of Engineering
Brown University, Providence, RI, USA
Phone: 401.863.1531, Fax: 401.863.9039
Email: GeneralChair@tttc-itsw.org

Submit extended abstracts via email to:
Abhijit Jas, Program Chair
Design and Technology Solutions
Intel Corporation, Austin, TX 78746
Phone: 512.732.3978, FAX: 512.732.3912
Email: ProgramChair@tttc-itsw.org

Committees

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General Chair
J. Dworak – Brown U.

Past Chair
N. Mukherjee – Mentor Graphics

Vice Chair
S. Chakravarty - LSI

Program Chair
A. Jas – Intel

Panels Chair
S. Khatri – Texas A&M U.

Embedded Tutorials Chair
V. Chickermane - Cadence

Publicity Chair
B. Foutz – Cadence

Finance Chair
S. Patil – Intel

Local Arrangements Chair
N. Touba – U. Texas, Austin

European Liaison
M. Zwolinski – U. Southampton

Asian Liaison
C. W. Wu – Nat. Tsing Hua U.

Program Committee
M. Abadir – FreeScale
R. Aitken – ARM
K. Balakrishnan – AMD
C. Barnhart – SiliconAid
K. Chakrabarty – Duke U.
K.-T.Cheng – UC Santa Barbara
A. Crouch – Asset-Intertech
R. Datta – TI
S. Davidson – Sun Micro.
C. Dixit – LSI
A. Guettaf – Broadcom
M. Hsiao – Virginia Tech.
K. Iwasaki – Tokyo Metro. U.
R. Kapur – Synopsys
M. Laisne – QualComm
K.-J. Lee – Nat. Cheng-Kung U.
A. Majumdar – Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U.
M. Nourani –U. Texas, Dallas
A. Orailoglu – UC San Diego
B. Pouya – Freescale
J. Qian – Cisco
J. Rajski – Mentor Graphics
S. M. Reddy – U. Iowa
M. Tahoori – Northeastern U.
S. Tragoudas – S. Illinois U.
H. Walker – Texas A&M U.
Li-C. Wang – UC Santa Barbara

For more information, visit us on the web at: http://www.tttc-itsw.org

TheInternational Test Synthesis Workshop (ITSW 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	16th International Test Synthesis Workshop (ITSW 2009) March 23-25, 2009 University of Texas at Austin Austin, Texas, USA http://www.tttc-itsw.org